multiple constant drivers for net erro

reg signed  final_additions ;  // two multiply results added together and registered
reg signed  final_result;  // sum of final_additions
wire signed  final_result_temp;
wire signed  coefficients ;     
 
genvar Counter_Result;
                generate
                for(Counter_Result = 0; Counter_Result < ((NUM_OF_TAPS/4)-1); Counter_Result=Counter_Result+1)
                begin : the_final_reult
                                always @ (posedge clk or posedge reset)
                                begin
                                                if (reset)
                                                begin
                                                                final_result_temp<= 0;
                                                end
                                                else if (clear == 1)
                                                begin
                                                                final_result_temp <= 0;
                                                end
                                                if (Counter_Result == 0)
                                                begin
                                                                final_result_temp <= final_additions;
                                                end
                                                else
                                                begin
                                                                final_result_temp <= final_result_temp+final_additions;
                                                end
                                end
                end
                endgenerate
                always @ (posedge clk or posedge reset)
                begin
                                if (reset)
                                begin
                                                final_result <= 0;
                                end
                                else if (clear == 1)
                                begin
                                                final_result <= 0;
                                end
                                else
                                begin
                                                final_result <= final_result_temp;
                                end
                end

Thank you for your helps.

well you don't need those stages but if you are happy fair enough. The generate statement with (n) count tells the compiler to create designs (n) times. It is just a short way of writing code. The design will not create counter but just use it during compile time and the counter will then vanish from this world while any target signal repeated in the generate loop will complain of multiple drivers each pushing it one way or the other.

I remove a generate statement but i get the same error.

Then you must show your code and where else you are driving(not reading) the final_result.

Delaration of the variable

        reg signed  taps ;
    reg signed  initial_additions ;  // addition between two taps, only used in symetric filters
    reg signed  multiplications ; // initial_additions * coefficients
    reg signed  final_additions ;  // two multiply results added together and registered
    reg signed  final_result;  // sum of final_additions
    wire signed  final_result_temp;
    wire signed  coefficients ;
    wire signed  Counter_Result=0;

    always @ (posedge clk or posedge reset)
    begin
        if (reset)
        begin
            final_result <= 0;
        end
        else if (clear == 1)
        begin
            final_result <= 0;
        end
        else
        begin
        final_result_temp<=final_result_temp+final_additions;
Counter_Result<=Counter_Result+1;
        if (Counter_Result==((NUM_OF_TAPS/4)-1))
        begin
            final_result <= final_result_temp;
            final_result_temp <= 0;
            Counter_Result=0;
        end    
        end
    end

scfifo the_output_fifo (
        .aclr (reset),
        .sclr (clear),
        .clock (clk),
        .data (final_result),
        .almost_full (fifo_half_full),
        .empty (fifo_empty),
        .q (source_data),
        .rdreq (read_fifo),
        .wrreq (tag)  // tag delay pipeline matches when valid data pops out of "final_result"
    );

where do you count up. Is the multiple drive on counter now?

I think you edited and added counter later. Is the multiple drive on final_result or somewhere else?