Honored Contributor
Honored Contributorwell you don't need those stages but if you are happy fair enough. The generate statement with (n) count tells the compiler to create designs (n) times. It is just a short way of writing code. The design will not create counter but just use it during compile time and the counter will then vanish from this world while any target signal repeated in the generate loop will complain of multiple drivers each pushing it one way or the other.
so just run your counter and add up according to its value to index the temp result without generate. At least that is how vhdl works and assume verilog will not be that different.
