multiple constant drivers for net erro

Delaration of the variable

        reg signed  taps ;
    reg signed  initial_additions ;  // addition between two taps, only used in symetric filters
    reg signed  multiplications ; // initial_additions * coefficients
    reg signed  final_additions ;  // two multiply results added together and registered
    reg signed  final_result;  // sum of final_additions
    wire signed  final_result_temp;
    wire signed  coefficients ;
    wire signed  Counter_Result=0;

    always @ (posedge clk or posedge reset)
    begin
        if (reset)
        begin
            final_result <= 0;
        end
        else if (clear == 1)
        begin
            final_result <= 0;
        end
        else
        begin
        final_result_temp<=final_result_temp+final_additions;
Counter_Result<=Counter_Result+1;
        if (Counter_Result==((NUM_OF_TAPS/4)-1))
        begin
            final_result <= final_result_temp;
            final_result_temp <= 0;
            Counter_Result=0;
        end    
        end
    end

scfifo the_output_fifo (
        .aclr (reset),
        .sclr (clear),
        .clock (clk),
        .data (final_result),
        .almost_full (fifo_half_full),
        .empty (fifo_empty),
        .q (source_data),
        .rdreq (read_fifo),
        .wrreq (tag)  // tag delay pipeline matches when valid data pops out of "final_result"
    );