multiple constant drivers for net erro

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Hi,

I have this code

reg signed  final_additions ;  // two multiply results added together and registered
reg signed  final_result;  // sum of final_additions
wire signed  final_result_temp;
wire signed  coefficients ;     
 
genvar Counter_Result;
                generate
                for(Counter_Result = 0; Counter_Result < ((NUM_OF_TAPS/4)-1); Counter_Result=Counter_Result+1)
                begin : the_final_reult
                                always @ (posedge clk or posedge reset)
                                begin
                                                if (reset)
                                                begin
                                                                final_result_temp<= 0;
                                                end
                                                else if (clear == 1)
                                                begin
                                                                final_result_temp <= 0;
                                                end
                                                if (Counter_Result == 0)
                                                begin
                                                                final_result_temp <= final_additions;
                                                end
                                                else
                                                begin
                                                                final_result_temp <= final_result_temp+final_additions;
                                                end
                                end
                end
                endgenerate
                always @ (posedge clk or posedge reset)
                begin
                                if (reset)
                                begin
                                                final_result <= 0;
                                end
                                else if (clear == 1)
                                begin
                                                final_result <= 0;
                                end
                                else
                                begin
                                                final_result <= final_result_temp;
                                end
                end

When i launch the compilation i get this error:

Error (10028): Can't resolve multiple constant drivers for net "final_result[33]" at custom_FIR.v(255).

How can i correct this erros.

Thank you

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Do you drive "final_result" anywhere else not shown in your code?

I haven't done verilog for years but I believe you don't need generate as you are driving the same signals several times. since you want to add up all the additions in an accumulator in real time then I will run a hard counter and add according to its value. The generate statement is a compile time issue, isn't it?