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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multicylcle Constraints with TimeQuest

Hey everybody!

I have a serious problem with appying multicycle contraints to my design and would be glad if somebody could help me out with this:

Basically i want to use the multicylcle path to save pipeline registers in a signal processing application.

There is a "source" register which is loaded with a dword every now and then and a "sink" register, which is enabled some clock periods after the source register was loaded to give the combinatoric some time to calculate the stable result.

A fsm controls the enable logic, loading the new dword into source, waiting a few clock periods, before enabling the sink to capture the valid result.

So my contraints look something like this to tell Timequest, that the combi path between source and sink can take longer than 1 clk period. The sink register is enabled after 4 clocks to latch the result:

set_multicycle_path -to [get_registers SINK_DFF*}] -setup -end 4

set_multicycle_path -to [get_registers SINK_DFF*}] -hold -end 4

However i am experiencing random errors all the time which hints to a timing problem... Time Quest indicates no errors whatsoever...

Both registers and the fsm are running with the same clock which is of course

known to TimeQuest via the create_clock command.

Its basically just two regs and a long combi path between them...

What am I doing wrong here?

Thanks in advance,

Cheers,

Tim

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I am still learning the syntax and rules of TimeQuest but I believe your command should be like this:

    set_multicycle_path -setup -end -from [get_pins reg1|clk] -to [get_pins reg2|*] 4

    As indicated by altera example for two register path(TimeQuest design examples). Your example is more like that for one clk...

    You must also be careful about multicycle validity. If your register is enabled every 4 clks it doesn't mean automatically that it is a valid case. If its D input is launched regularly every 4 clks then that is a valid case but if some other signals share the drive on thIs D input then it may not be valid.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The hold multicycle looks too relaxed. Change the hold multicycle value to 3 and see if you get a hold violation.

    Hold multicycle values in SDC start at 0 (the default hold check), which is usually one clock edge before the setup's latching edge. Therefore, to perform a hold check against the launching edge (i.e., a hold relationship of zero), use the setup multicycle value minus 1.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    I am still learning the syntax and rules of TimeQuest but I believe your command should be like this:

    set_multicycle_path -setup -end -from [get_pins reg1|clk] -to [get_pins reg2|*] 4

    As indicated by altera example for two register path(TimeQuest design examples). Your example is more like that for one clk...

    --- Quote End ---

    In "proper" SDC, yes, you constraint from a clock pin to a data pin as shown. You can, of course, drop the -from if you want to constraint all paths to the register. However, TimeQuest also allows you to specify the register itself as opposed to the data pins using the get_registers command, as timbenneckenstein has done. Therefore, the constraint is perfectly valid.

    However...

    The multicycle constraint is likely catching the enable signal from the FSM as well, and that path is likely a single-cycle path. You can correct it with an additional multicycle, such as:

    set_multicycle_path -to [get_pins SINK_DFF|ena] -setup -end 1

    set_multicycle_path -to [get_pins SINK_DFF|ena] -hold -end 0

    Or you can make your multicycles more restrictive by specifying the -from nodes.

    Or use the clock-enable multicycle example at:

    http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    All right Gopher!

    Yeah that was the problem... The multicycle contraint not only included the data path but also the FSM CLK enable... even though it was of course supposed to be a single cycle path...

    Thank you very much!

    Tim