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Altera_Forum's avatar
Altera_Forum
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13 years ago

multicycle setup of 2 work, of 4 not!

hi, i did a clock enable like the example given by altera http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html

to run my design at half frequency 50 MHz

the clock enable is generated like in the example, negate a signal every clock.

in my design i have a state machine driven by this clock enable that manipulate some big std_logic_vectors.

This work! But the setup slack is poor so...

i tried to slow down @ 25 MHz, this time, the enable is derived from a counter:

process(clk)

begin

if rising_edge(clk)

if count = "11" then

enable_reg<= '1';

else

enable_reg <= '0';

count <= count +1;

end if;

end if;

end process;

i modified the constraints:

# Setup multicycle of 4 to enabled driven destination registers

set_multicycle_path 4 -to [get_fanouts [get_pins enable_reg|q*]

-through [get_pins -hierarchical *|*ena*]] -end -setup

#Hold multicycle of 3 to enabled driven destination registers

set_multicycle_path 3 -to [get_fanouts [get_pins enable_reg|q*]

-through [get_pins -hierarchical *|*ena*]] -end –hold

and this time i failed to meet constraint!!

why? is because the enable is generated by a counter?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    clock enable from any logic should be ok as long as it is generated in same clock domain as its target registers. I take it you have connected clokenable correctly after clock edge statements. If so timing will be relaxed in that area.

    If you it gets worse then it could be somewhere else you have a bottleneck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    i changed only the clock enable logic and the multicycle constraints so if a bottleneck is present, it should be more present with multicycle of 2 instead of 4 no?.

    the failed path when i use multicycle of 4, is a signal inside the FSM that have the clock enable

    the setup relationship from time quest timing analyzer is 10ns for this path and not 40 ns!

    this is the operation, from "dividend" to "dividend":

    dividend <= (not dividend) + 1;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    i think i found the problem.

    i watched with the rtl viewer and i see that the registers inside the FSM have not the enable driven by my clk_en but from the reset!

    So my multicycle constraint isn't applied to the majority of nets.

    I usually write processes like:

    process(clk_i)

    begin

    if rising_edge(clk_i) then

    if reset = '1' then

    register <= '0';

    elsif clk_en = '1' then

    if condition_1 = '1' then

    ---operations

    end if;

    end if;

    end if;

    end process;

    i think this way should be used with xilinx flip flop, not for altera.

    How do i code it correctly?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    found from Altera Recommended HDL Coding Styles:

    --- Quote Start ---

    If you code a register with a synchronous clear signal that has priority over the clock enable signal, the software must emulate the clock enable functionality using data inputs to the registers.

    Because the signal does not use the clock enable port of a

    register, you cannot apply a clock enable multicycle constraint.

    In this case, following the priority of signals available in the device is clearly the best choice for the priority

    of these control signals, and using a different priority causes unexpected results with an assignment to the clock enable signal.

    --- Quote End ---