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Altera_Forum's avatar
Altera_Forum
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13 years ago

multicycle setup of 2 work, of 4 not!

hi, i did a clock enable like the example given by altera http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html to run my design at half frequency 50 MHz the clock enabl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

clock enable from any logic should be ok as long as it is generated in same clock domain as its target registers. I take it you have connected clokenable correctly after clock edge statements. If so timing will be relaxed in that area.

If you it gets worse then it could be somewhere else you have a bottleneck.