multicycle setup of 2 work, of 4 not!

found from Altera Recommended HDL Coding Styles:

--- Quote Start ---

If you code a register with a synchronous clear signal that has priority over the clock enable signal, the software must emulate the clock enable functionality using data inputs to the registers.

Because the signal does not use the clock enable port of a

register, you cannot apply a clock enable multicycle constraint.

In this case, following the priority of signals available in the device is clearly the best choice for the priority

of these control signals, and using a different priority causes unexpected results with an assignment to the clock enable signal.

--- Quote End ---