multicycle setup of 2 work, of 4 not!

i think i found the problem.

i watched with the rtl viewer and i see that the registers inside the FSM have not the enable driven by my clk_en but from the reset!

So my multicycle constraint isn't applied to the majority of nets.

I usually write processes like:

process(clk_i)

begin

if rising_edge(clk_i) then

if reset = '1' then

register <= '0';

elsif clk_en = '1' then

if condition_1 = '1' then

---operations

end if;

end if;

end if;

end process;

i think this way should be used with xilinx flip flop, not for altera.

How do i code it correctly?