Forum Discussion
Altera_Forum
Honored Contributor
13 years agoi changed only the clock enable logic and the multicycle constraints so if a bottleneck is present, it should be more present with multicycle of 2 instead of 4 no?.
the failed path when i use multicycle of 4, is a signal inside the FSM that have the clock enable the setup relationship from time quest timing analyzer is 10ns for this path and not 40 ns! this is the operation, from "dividend" to "dividend": dividend <= (not dividend) + 1;