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Altera_Forum's avatar
Altera_Forum
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12 years ago

module top (SW[0]) complains but module top(SW) doesn't? Why?

Hi,

I'm using Cyclone III on DE0, Quartus II.

I was wondering where/how are the groupings of SW[0] to SW[9] done and combined into one signal of 10 bits named SW?

Initially, I defined SW[0] to the appropriate pin myself and got no complaint.

Later, I used import on the default .qsf file from Altera website and I get the complaint "some pins have incomplete i/o assignment" if I try to use

module top (SW[0], LEDG[0])

instead of

module top (SW, LEDG)

I would just like to understand what is going on.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Sorry maybe my question is no good. I'm looking at the DE0 schematic and it appears the name of the bus is SW/LEDG and contains [9:0].

    Can anyone confirm if it is possible to use module top(SW[0], LEDG[0]); input SW[0]; output LEDG[0]; ?

    Where I assign SW[0] and LEDG[0] to PIN_J6 and PIN_J1 respectively? The functionality desired is a simple assign LEDG[0] = SW[0]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    module top (
input wire  SW,
output wire  LED
);
assign LED = SW;
endmodule

    or 

    module top (SW, LED);
input  SW;
output  LED;
wire  LED;
assign LED = SW;
endmodule

    Having analysed your code with Quartus the Pin Planner will present you with two 10-bit busses for you to assign pins to.

    Regards,

    Alex