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Altera_Forum's avatar
Altera_Forum
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12 years ago

module top (SW[0]) complains but module top(SW) doesn't? Why?

Hi, I'm using Cyclone III on DE0, Quartus II. I was wondering where/how are the groupings of SW[0] to SW[9] done and combined into one signal of 10 bits named SW? Initially, I defined...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

module top (
input wire  SW,
output wire  LED
);
assign LED = SW;
endmodule

or 

module top (SW, LED);
input  SW;
output  LED;
wire  LED;
assign LED = SW;
endmodule

Having analysed your code with Quartus the Pin Planner will present you with two 10-bit busses for you to assign pins to.

Regards,

Alex