Altera_Forum
Honored Contributor
Honored Contributormodlesim 6.6d
i am new to modlesim, i downloaded the latest version, i hope if someone tells me how to simulate vhdl program with modlesim in simple way
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19 Replies
Altera_ForumUse these commands in the command window, or in a .do file:
vcom <my_vhdl_file> vsim <my_entity> run 1ms- Altera_Forum
thanks for the reply,
how can i enter some vlaues to my inputs to see the repose of the outputs in modlesim - Altera_Forum
You need to write a testbench in HDL.
- Altera_Forum
is there any way we can force the inputs to be 1 or 0 and see the output, if not how to write testbench in HDL
- Altera_Forum
you can only do inputs via a testbench.
A testbench is just an HDL file, like any other, that instantiates your unit under test. - Altera_Forum
how to write this HDL file, is it done by the modlesim, or i have to create it, is there any information may help me in this
- Altera_Forum
Its just a text file. What language is your design in?
- Altera_Forum
if you mean the vhd file that i am simulating, it is already created and i am simulating it , or u mean different file beside the VHDL code program with extension vhd
- Altera_Forum
the testbench is a completly separate VHDL file from your design - used only for the purpose of testing. Because it will not get synthesised, you can do all sorts of things you would otherwise not be allowed to do.
For example, to generate a clock, you can do this: --100 MHz clock signal clk : std_logic := '1'; ... clk <= not clk after 5 ns; you then create the other input signals however you want and connect them to the design under test, and then run the testbench in Modelsim. I think Quartus can create a testbench for you, but I usually just create them myself. - Altera_Forum
THE program written in VHDL codes by using quartusII
