modlesim 6.6d

the testbench is a completly separate VHDL file from your design - used only for the purpose of testing. Because it will not get synthesised, you can do all sorts of things you would otherwise not be allowed to do.

For example, to generate a clock, you can do this:

--100 MHz clock

signal clk : std_logic := '1';

...

clk <= not clk after 5 ns;

you then create the other input signals however you want and connect them to the design under test, and then run the testbench in Modelsim.

I think Quartus can create a testbench for you, but I usually just create them myself.