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Altera_Forum's avatar
Altera_Forum
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14 years ago

modlesim 6.6d

i am new to modlesim, i downloaded the latest version, i hope if someone tells me how to simulate vhdl program with modlesim in simple way
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

is there any way we can force the inputs to be 1 or 0 and see the output, if not how to write testbench in HDL