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Altera_Forum
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15 years ago

ModelSim undefined initial value

Hello, I am trying to do some simple simulation using modelsim-altera and am seeing undefined value for output "result" and it stays like that until 10ns or so into the simulation. Here is the example:

counter.v 

module counter (clk, reset, result);
input clk;
input reset;
output reg  result;
initial# 0 result = 0;
always @(posedge clk or posedge reset)
begin
   if (reset)
      result   <= 0;
   else
      result   <= result + 1'b1;
end
endmodule

counter_tb 


`timescale 1ns/1ps
module counter_tb ();
reg clk;
reg reset;
wire  result;
counter u_count (clk, reset, result);
initial
begin
  # 0 clk   = 0;
   
  # 0 reset = 1;
  # 100 reset = 0;
end
always# 2.5 clk = ~clk;
endmodule

The waveform is shown in the attached jpeg. This happens when I select Gate Level Simulation. Any ideas why "result" is undefined?

Thank you

15 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    1) Initial block are sythesized by Quartus. Of course not every construct in an initial block can be sythesized, but assigning power-up values to registers is valid. Many people however, don't like to use power-up values, they use reset instead.

    2) An external reset is not mandatory, most designs can use an internal one.

    3) Just forget about gate level simulation. Use static timing analysis and RTL level simulation.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    That kind of makes it hard to make sure that a design with no external reset function properly.

    --- Quote End ---

    As I mentioned in my initial post, your testcode is inappropriate to check the function of the power on reset. You're doing effectívely all at once: Starting the clock and asserting the external reset. In this situation, you can't see the initial power-on state at all.

    A clock that is already present during power-on may cause timing violations in comibination with the asynchronous release of the internal reset. In this case, an initial counter or state machine state can become unpredictable.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I did try to delay the clock and the reset signal. I played with combinations of both but could never get the count to settle before the 5ns mark. I will change counter.v a little bit next.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think you are complicating yourself too much. Once again, forget about gate-level/timing simulation.

    The output should not be undefined. It is probably an artifact of non-accurate gate-level simulation, combined with non-recommended testbench practices. In particular, avoid using a zero delay, just don't use any delay at all in that case, and use non-blocking assignments.

    But yet once again, I'd avoid gate-level simulation altogether.