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That kind of makes it hard to make sure that a design with no external reset function properly.
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As I mentioned in my initial post, your testcode is inappropriate to check the function of the power on reset. You're doing effectívely all at once: Starting the clock and asserting the external reset. In this situation, you can't see the initial power-on state at all.
A clock that is already present during power-on may cause timing violations in comibination with the asynchronous release of the internal reset. In this case, an initial counter or state machine state can become unpredictable.
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