Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI think you are complicating yourself too much. Once again, forget about gate-level/timing simulation.
The output should not be undefined. It is probably an artifact of non-accurate gate-level simulation, combined with non-recommended testbench practices. In particular, avoid using a zero delay, just don't use any delay at all in that case, and use non-blocking assignments. But yet once again, I'd avoid gate-level simulation altogether.