Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorModelsim: top module not testbench
Hi. I was trying to run the simulation using native link method. When the modelsim in simulation mode, the top module always is the design module instead of testbench.
in the .do file, vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L cycloneiii_ver -L rtl_work -L work -voptargs="+acc" FIR_Signal_Storage_RAM, i try to change it to ... FIR_Signal_Storage_RAM_tb but in vain. Whenever, i click run eda RTL simulation, it will automatically change it to FIR_Signal_Storage_RAM. How to correct it? thanks7 Replies
Altera_ForumHey I think you may be having a problem I've had and wanted to post up my solution even if it is not correct. If nothing else, to help others who run across this searching.
Anyways, the problem (that I think you guys are having) I had was that I would generate a testbench and make the stimulus mods I need with no problems, but when I launch Modelsim through the RTL simulation menu it would load my top level design module and the signals would always be red/unkoown. This is because it wouldn't load my testbench as the top level module in modelsim to generate any of my stimulus files. If you go to library -> work and right click and tell modelsim to simulate the test bench it will re-run and things would work. So, to solve this problem what you need to do is specify your "top level" in the "edit test bench settings" in your testbench editor in quartus to be the testbench. When you use the quartus testbench generator it has a tendency to generate a testbench with the same name as your top level and then modelsim launches on the top level design. Here is a screen shot of what I'm talking about: https://www.alteraforum.com/forum/attachment.php?attachmentid=8997 Long story short: Right click on your I2C_Controller -> Settings -> (on the left select EDA Tool Settings/Simulation) -> Compile Testbench -> Test Benches button -> New/Edit (depends on if you already added one) -> Set your "top level module in test bench" as the top level entity in the TEST BENCH file NOT your top level in your actual design. Hope this helps someone. Rob- Altera_Forum
Hi, the top level module, or rather the testbench must be set in the settings->EDA tool options->Simulation->Native Link Settings-> testbenches-> new / edit
The top level name used in the .do is taken from the settings for the Testbench, Name (just a name), Top level module in test bench (entity name of testbench), Design instance (instance name of UUT). - Altera_Forum
it helps. thanks
- Altera_Forum
I have exactly the same question as yours. Could you please tell me how to correct the top level module in modelsim-altera?
- Altera_Forum
Hi,
Please see my last post. If you are running the simulation using Native Link (launching via the tools-> Run Simualtion Tool. The options passed to the generated scripts come from the Assignments->Settings->Simulation menu. Please ensure your have followed the flow: 1. Select "Compile a testbench" 2. Press the "test benches" button 3. create new 4. correctly specified the details (module names) 5. Add your testbench files in the Test bench files section. - Altera_Forum--- Quote Start --- Hi, Please see my last post. If you are running the simulation using Native Link (launching via the tools-> Run Simualtion Tool. The options passed to the generated scripts come from the Assignments->Settings->Simulation menu. Please ensure your have followed the flow: 1. Select "Compile a testbench" 2. Press the "test benches" button 3. create new 4. correctly specified the details (module names) 5. Add your testbench files in the Test bench files section. --- Quote End --- Thank you but it doesn't work. It seems like Quartus is able to write the correct testbench with the correct top level module name, but when it comes to Modelsim, top level module entry becomes incorrect. Note that I am using a RAM module generated by megawizard in my design, and I suppose woeichee was using one as well (FIR_Signal_Storage_RAM). So I was wondering there might be some problems of Modelsim simulating designs which includes megawizard generated module.
- Altera_Forum
it is the same as QuartusPenguin suggested in his first post:
--- Quote Start --- "The top level name used in the .do is taken from the settings for the Testbench, Name (just a name), Top level module in test bench (entity name of testbench), Design instance (instance name of UUT)." --- Quote End --- top level module in test bench = ENTITY NAME OF TESTBENCH (in case of VHDL). (If you're automativally generating testbenches with Quartus Prime's Testbench Writer then it is 'your-design-name_vhd_tst'). Again top level module in test bench is not entity name of top module (i.e. your design), it is the name of the testbench entity specified in your testbench file.
