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Altera_Forum's avatar
Altera_Forum
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16 years ago

Modelsim: top module not testbench

Hi. I was trying to run the simulation using native link method. When the modelsim in simulation mode, the top module always is the design module instead of testbench. in the .do file, v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

it is the same as QuartusPenguin suggested in his first post:

--- Quote Start ---

"The top level name used in the .do is taken from the settings for the Testbench, Name (just a name), Top level module in test bench (entity name of testbench), Design instance (instance name of UUT)."

--- Quote End ---

top level module in test bench = ENTITY NAME OF TESTBENCH (in case of VHDL).

(If you're automativally generating testbenches with Quartus Prime's Testbench Writer then it is 'your-design-name_vhd_tst').

Again top level module in test bench is not entity name of top module (i.e. your design), it is the name of the testbench entity specified in your testbench file.