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Altera_Forum's avatar
Altera_Forum
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13 years ago

ModelSim component : Instantiation of an instance failed

An instantiation in my code is failing with the error message

Error: (vsim-3039) ../design/mdct/DCT1D.vhd(155): Instantiation of 'FinitePrecRndNrst' failed.

Following is the failing code block

U_FinitePrecRndNrst : FinitePrecRndNrst

generic map(

C_IN_SZ => DA_W,

C_OUT_SZ => DA_W-12,

C_FRAC_SZ => 12

)

port map(

CLK => clk,

RST => rst,

datain => dcto_4,

dataval => ramwe_d4,

dataout => fpr_out,

clip_inc => open,

dval_out => ramwe

);

============================================

The definition of FinitePrecRndNrst is like this:

component FinitePrecRndNrst is

generic

(

C_IN_SZ : natural := 37;

C_OUT_SZ : natural := 16;

C_FRAC_SZ : natural := 15

);

port (

CLK : in std_logic;

RST : in std_logic;

datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);

dataval : in std_logic;

dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);

clip_inc : out std_logic;

dval_out : out std_logic

);

====================================================

This code is something which i am testing so would appreciate any help in why this is happening.

Thank you !!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Sure, here goes ....

    When I try to run the specifc module, the complete error is as follows

    # vsim work.dct1d

    # Loading std.standard

    # Loading std.textio(body)

    # Loading ieee.std_logic_1164(body)

    # Loading ieee.numeric_std(body)

    # Loading work.mdct_pkg

    # Loading work.dct1d(rtl)

    # PE Student Edition supports only a single HDL

    # ** Error: (vsim-3039) ../design/mdct/DCT1D.vhd(155): Instantiation of 'FinitePrecRndNrst' failed.

    #

    # Region: /dct1d

    # Error loading design

    # Error: Error loading design

    # Pausing macro execution

    # MACRO ./sim.do PAUSED at line 3

    The relevant section in DCT1D.vhd is as follows (as specified above)

    U_FinitePrecRndNrst : FinitePrecRndNrst

    generic map(

    C_IN_SZ => DA_W,

    C_OUT_SZ => DA_W-12,

    C_FRAC_SZ => 12

    )

    port map(

    CLK => clk,

    RST => rst,

    datain => dcto_4,

    dataval => ramwe_d4,

    dataout => fpr_out,

    clip_inc => open,

    dval_out => ramwe

    ); -- This is line 155

    Thanks !

    -
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    # PE Student Edition supports only a single HDL

    Theres your problem. FinitePrecRndNrst is probably a Verilog module
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    # PE Student Edition supports only a single HDL

    Theres your problem. FinitePrecRndNrst is probably a Verilog module

    --- Quote End ---

    Yeah, pretty much what I thought .... Thanks for the confirmation.

    I am playing around with some verlilog to VHDL conversion tools and see if recompiling them will bring some joy ....

    Thanks again !