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Altera_Forum
Honored Contributor
13 years agoSure, here goes ....
When I try to run the specifc module, the complete error is as follows # vsim work.dct1d # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.mdct_pkg # Loading work.dct1d(rtl) # PE Student Edition supports only a single HDL # ** Error: (vsim-3039) ../design/mdct/DCT1D.vhd(155): Instantiation of 'FinitePrecRndNrst' failed. # # Region: /dct1d # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./sim.do PAUSED at line 3 The relevant section in DCT1D.vhd is as follows (as specified above) U_FinitePrecRndNrst : FinitePrecRndNrst generic map( C_IN_SZ => DA_W, C_OUT_SZ => DA_W-12, C_FRAC_SZ => 12 ) port map( CLK => clk, RST => rst, datain => dcto_4, dataval => ramwe_d4, dataout => fpr_out, clip_inc => open, dval_out => ramwe ); -- This is line 155 Thanks ! -