ModelSim-Altera vsim-3584 error during Gate-Level Simulation (Verilog)

Hi Thread,

Did you figure out it? I have the same problem and I haven't worked out it. :cry:

Thanks,

Luana

--- Quote Start ---

I'm trying to do gate-level simulation of a module and get the following error related to a module parameter I have defined:

# Loading work.mod_M_counter_v
#  Loading work.mod_M_counter
#  Loading cycloneii_ver.cycloneii_io
#  Loading cycloneii_ver.cycloneii_mux21
#  Loading cycloneii_ver.cycloneii_dffe
#  Loading cycloneii_ver.cycloneii_asynch_io
#  Loading cycloneii_ver.cycloneii_clkctrl
#  Loading cycloneii_ver.cycloneii_mux41
#  Loading cycloneii_ver.cycloneii_ena_reg
#  Loading cycloneii_ver.cycloneii_lcell_comb
#  Loading cycloneii_ver.cycloneii_lcell_ff
#  ** Error: (vsim-3584) C:/altera/13.0sp1/Learning/Test Benches/mod_M_counter_v.v(30): Module parameter 'M' not found for override.

The simulation works correctly for RTL Simulation. I'm using Quartus II 13.0.1 and ModelSim-Altera 10.1d. The module is defined using:

module mod_M_counter
    # (parameter M=10)
     (
         input clk,
         input reset,
         output tick,
         output  out
    );

and the simulation instantiates the module using the following (which is where the error is occurring):

    mod_M_counter# (.M(10)) uut (
        .clk(clk),
        .reset(reset),
        .tick(tick),
        .out(out)
    );

Any help with what I am missing? Thanks!

--- Quote End ---

Yeah, so the issue is that gate-level simulation is performed after place and route so the development environment has already compiled and defined the parameter.. It can't be changed/assigned in the testbench because the design has already been synthesized and routed.

The workaround would be to define the default parameter for the module to be whatever you want for your testbench, synthesize, and then call the default module instantiation in the testbench rather than the parameterized one.

I'm a bit of a beginner so I don't know any more elegant way :-)