ModelSim-Altera vsim-3584 error during Gate-Level Simulation (Verilog)

Yeah, so the issue is that gate-level simulation is performed after place and route so the development environment has already compiled and defined the parameter.. It can't be changed/assigned in the testbench because the design has already been synthesized and routed.

The workaround would be to define the default parameter for the module to be whatever you want for your testbench, synthesize, and then call the default module instantiation in the testbench rather than the parameterized one.

I'm a bit of a beginner so I don't know any more elegant way :-)