ModelSim-Altera vsim-3584 error during Gate-Level Simulation (Verilog)

Hi Thread,

Did you figure out it? I have the same problem and I haven't worked out it. :cry:

Thanks,

Luana

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I'm trying to do gate-level simulation of a module and get the following error related to a module parameter I have defined:

# Loading work.mod_M_counter_v
#  Loading work.mod_M_counter
#  Loading cycloneii_ver.cycloneii_io
#  Loading cycloneii_ver.cycloneii_mux21
#  Loading cycloneii_ver.cycloneii_dffe
#  Loading cycloneii_ver.cycloneii_asynch_io
#  Loading cycloneii_ver.cycloneii_clkctrl
#  Loading cycloneii_ver.cycloneii_mux41
#  Loading cycloneii_ver.cycloneii_ena_reg
#  Loading cycloneii_ver.cycloneii_lcell_comb
#  Loading cycloneii_ver.cycloneii_lcell_ff
#  ** Error: (vsim-3584) C:/altera/13.0sp1/Learning/Test Benches/mod_M_counter_v.v(30): Module parameter 'M' not found for override.

The simulation works correctly for RTL Simulation. I'm using Quartus II 13.0.1 and ModelSim-Altera 10.1d. The module is defined using:

module mod_M_counter
    # (parameter M=10)
     (
         input clk,
         input reset,
         output tick,
         output  out
    );

and the simulation instantiates the module using the following (which is where the error is occurring):

    mod_M_counter# (.M(10)) uut (
        .clk(clk),
        .reset(reset),
        .tick(tick),
        .out(out)
    );

Any help with what I am missing? Thanks!

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