ModelSim-Altera supports AHDL code?

No. Only Quartus supports AHDL. You can only do a post place and route timing simulation in modelsim with AHDL (and I think thats what the old quartus simulator did too)

I suggest switching to Verilog or VHDL.

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No. Only Quartus supports AHDL. You can only do a post place and route timing simulation in modelsim with AHDL (and I think thats what the old quartus simulator did too)

I suggest switching to Verilog or VHDL.

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Up to Quartus 9.2sp1 you could run either Functional or Timing simulation with the built-in simulator. I guess, just like Tricky, that most people ran the Timing one (I did ...).

If you enable the VHDL or Verilog netlist writer (in Quartus II) you can simulate your design in AHDL by running ModelSim in Gate Timing simulation. I did it some months ago for an old project and it worked quite nicely. I felt that the ModeSim ASE was even faster than the internal simulator.

i agree, the way to do it is a Post-Map simulation. you can configure EDA Netlist Writer to output a post-map netlist. you won't get visibility into the internal signals and it will be slower than a pure RTL simulation, but it will work

in the long term you should port to a newer HDL

Can I view the internal signals(nodes) using Quartus to simulate AHDL?

In VHDL, I can include the statements below to keep with desired signal and their original names, and then use Post-synthesis to find the signal.

attribute keep: boolean;

attribute keep of G: signal is true;

but is there the same syntax for AHDL?

I am converting the legacy AHDL to VHDL, but still need to simulate the legacy AHDL to understand the legacy design.

Thanks in advance.

The only way to simulate AHDL is with a post map simulation, so you're stuck with whatever the node names are. Afaik, there are no attributes similar for AHDL.

Have you tried the Xilinx xport tool? (it converts AHDL to VHDL or Verilog)