Forum Discussion
Altera_Forum
Honored Contributor
12 years agoCan I view the internal signals(nodes) using Quartus to simulate AHDL?
In VHDL, I can include the statements below to keep with desired signal and their original names, and then use Post-synthesis to find the signal. attribute keep: boolean; attribute keep of G: signal is true; but is there the same syntax for AHDL? I am converting the legacy AHDL to VHDL, but still need to simulate the legacy AHDL to understand the legacy design. Thanks in advance.