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No. Only Quartus supports AHDL. You can only do a post place and route timing simulation in modelsim with AHDL (and I think thats what the old quartus simulator did too)
I suggest switching to Verilog or VHDL.
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Up to Quartus 9.2sp1 you could run either Functional or Timing simulation with the built-in simulator. I guess, just like Tricky, that most people ran the Timing one (I did ...).
If you enable the VHDL or Verilog netlist writer (in Quartus II) you can simulate your design in AHDL by running ModelSim in Gate Timing simulation. I did it some months ago for an old project and it worked quite nicely. I felt that the ModeSim ASE was even faster than the internal simulator.
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