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Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone,

I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation. I have limited knowledge about quartus and VHDL and don't even know what can cause this error. I have been troubled by this problem for a week. Could someone please give me some help? Any idea is appreciated!

And here is my testbench:

LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY systemtb IS
END systemtb ;
ARCHITECTURE LogicFunction OF systemtb IS
COMPONENT system
port (start, clock, spike_1_1, spike_1_2, spike_1_3, spike_1_4, spike_1_5, spike_1_6, spike_1_7, spike_1_8, spike_1_9, spike_1_10, 
spike_1_11, spike_1_12, spike_1_13, spike_1_14, spike_1_15, spike_1_16,
spike_3_1, spike_3_2, spike_3_3, spike_3_4, spike_3_5, spike_3_6, spike_3_7, spike_3_8, spike_3_9, spike_3_10,
spike_3_11, spike_3_12, spike_3_13, spike_3_14, spike_3_15, spike_3_16: IN std_logic := '0';
target_x, target_y: in integer range 1 to 16;
reach_target: buffer std_logic := '0';
rounds:buffer integer := 0;
cur_in_1, cur_out_1, cur_in_2, cur_out_2: buffer integer range 0 to 16 := 0);
END COMPONENT ;
signal start: std_logic :='0';
signal spike_1_1, spike_1_2, spike_1_3, spike_1_4, spike_1_5, spike_1_6, spike_1_7, spike_1_8, spike_1_9, spike_1_10, 
spike_1_11, spike_1_12, spike_1_13, spike_1_14, spike_1_15, spike_1_16, 
spike_3_1, spike_3_2, spike_3_3, spike_3_4, spike_3_5, spike_3_6, spike_3_7, spike_3_8, spike_3_9, spike_3_10,
spike_3_11, spike_3_12, spike_3_13, spike_3_14, spike_3_15, spike_3_16: std_logic := '0';
signal clock: std_logic := '0';
signal cur_in_1, cur_out_1, cur_in_2, cur_out_2: integer range 0 to 16 := 0;
signal target_x: integer range 0 to 16 := 12;
signal target_y: integer range 0 to 16 := 4;
signal reach_target: std_logic := '0';
signal rounds: integer := 0;
signal times: integer := 0;
BEGIN
	l1: system port map (start, clock, spike_1_1, spike_1_2, spike_1_3, spike_1_4, spike_1_5, spike_1_6, spike_1_7, spike_1_8, spike_1_9, spike_1_10, 
spike_1_11, spike_1_12, spike_1_13, spike_1_14, spike_1_15, spike_1_16, 
spike_3_1, spike_3_2, spike_3_3, spike_3_4, spike_3_5, spike_3_6, spike_3_7, spike_3_8, spike_3_9, spike_3_10,
spike_3_11, spike_3_12, spike_3_13, spike_3_14, spike_3_15, spike_3_16,
target_x, target_y, reach_target, rounds, cur_in_1, cur_out_1, cur_in_2, cur_out_2);
	
	
	clock <= not clock after 12.5ns;
	
	statr: process
	begin
	start <= '0';
	wait for 1000 ns;
	start <= '1';
	times <= times + 1;
	wait for 3000 ns;
	start <= '0';
	wait for 20000 ns;
	end process;
	
	
	tb: process
	begin
	wait for 100 ns;
	spike_1_1 <= '1';
	spike_3_1 <= '1';
	spike_1_16 <= '0';
	spike_3_16 <= '0';
	wait for 100 ns;
	spike_1_1 <= '0';
	spike_3_1 <= '0';
	spike_1_2 <= '1';
	spike_3_2 <= '1';
	wait for 100 ns;
	spike_1_2 <= '0';
	spike_3_2 <= '0';
	spike_1_3 <= '1';
	spike_3_3 <= '1';
	wait for 100 ns;
	spike_1_3<= '0';
	spike_3_3 <= '0';
	spike_1_4 <= '1';
	spike_3_4 <= '1';
	wait for 100 ns;
	spike_1_4 <= '0';
	spike_3_4 <= '0';
	spike_1_5 <= '1';
	spike_3_5 <= '1';
	wait for 100 ns;
	spike_1_5 <= '0';
	spike_3_5 <= '0';
	spike_1_6 <= '1';
	spike_3_6 <= '1';
	wait for 100 ns;
	spike_1_6 <= '0';
	spike_3_6 <= '0';
	spike_1_7 <= '1';
	spike_3_7 <= '1';
	wait for 100 ns;
	spike_1_7 <= '0';
	spike_3_7 <= '0';
	spike_1_8 <= '1';
	spike_3_8 <= '1';
	wait for 100 ns;
	spike_1_8 <= '0';
	spike_3_8 <= '0';
	spike_1_9 <= '1';
	spike_3_9 <= '1';
	wait for 100 ns;
	spike_1_9 <= '0';
	spike_3_9 <= '0';
	spike_1_10 <= '1';
	spike_3_10 <= '1';
	wait for 100 ns;
	spike_1_10 <= '0';
	spike_3_10 <= '0';
	spike_1_11 <= '1';
	spike_3_11 <= '1';
	wait for 100 ns;
	spike_1_11 <= '0';
	spike_3_11 <= '0';
	spike_1_12 <= '1';
	spike_3_12 <= '1';	
	wait for 100 ns;
	spike_1_12 <= '0';
	spike_3_12 <= '0';
	spike_1_13 <= '1';
	spike_3_13 <= '1';	
	wait for 100 ns;
	spike_1_13 <= '0';
	spike_3_13 <= '0';
	spike_1_14 <= '1';
	spike_3_14 <= '1';	
	wait for 100 ns;
	spike_1_14 <= '0';
	spike_3_14 <= '0';
	spike_1_15 <= '1';
	spike_3_15 <= '1';	
	wait for 100 ns;
	spike_1_15 <= '0';
	spike_3_15 <= '0';
	spike_1_16 <= '1';
	spike_3_16 <= '1';	
	
	end process;
	
	
END;

Thanks a lot!

David

29 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    No. I am a student and doing some research with a professor. I actually just need to get the waveform to show my professor, since he has asked for that.

    --- Quote End ---

    Ok. Its worth making comments like that when you post. It helps the readers of the forum put the question in context and provides an estimate of where you may be in the learning curve.

    --- Quote Start ---

    I get what you are saying. That definitely is the correct way to test a design.

    --- Quote End ---

    Great. Many books on VHDL have very simplistic testbench examples - without clearly stating that the designs are simplistic.

    --- Quote Start ---

    I am actually implementing a searching & learning algorithm and the only thing that I care about is how many steps a learning agent takes to reach a target. I included the total steps in the waveform (for RTL simulation), and checked that manually... And I am also not checking my design with invalid inputs, since basically I am just doing all these to show that the algorithm can be implemented in hardware. So I only set input variables in my "testbench".

    --- Quote End ---

    As an "exercise for the student" I would recommend modifying your testbench to read the number of steps from your logic, and check it against the expected number of steps. Its a good habit to get into, so you may as well start out that way :)

    --- Quote Start ---

    I wrote the code and tested it with RTL simulation in last summer. And then I was waiting for the professor to get a board to test it in hardware. But now my professor has changed his mind and requested me to run post synthesis simulation to verify everything. So I have no choice but to get the waveform to show him:(

    --- Quote End ---

    Then show him you must! But appreciate that your supervisor might not be asking the right questions ... so ask him why, and try to get from him why he thinks seeing the gate-level netlist is important. He may not have a reason, and may assume that if that waveform looks correct, then the design is correct. However, if your waveforms do not exercise the path with the longest delay, you will not see a transition on the worst-case waveform. That is the whole point of performing a TimeQuest analysis - it tells you what the worst-case path is - and if that delay is less than you need, the design will work in real hardware.

    Supervisors are only human. They can only supervise based on their own experience. His may be a little rusty ... bottom line, is your supervisors job is to help you to learn for yourself. I think you're off to a good start, so as far as I am concerned (although he is asking you to produce the wrong data), he is doing his job just fine :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thank you Dave! I have one more question. Is there anything else other than Analysis & Synthesis Resource Usage Summary that can show the hardware usage of my design? My professor keeps asking me how many gates & chips will be needed, but that summary only tells how many ALUTs/LEs are used. Thanks.

    David
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    There are no gates on FPGAs, just LUTs. Luts can implement between one and several gates, as its just a look up table. So asking for "gate count" is pretty meaningless for an FPGA. And what are these "chips" you're on about?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    There are no gates on FPGAs, just LUTs. Luts can implement between one and several gates, as its just a look up table. So asking for "gate count" is pretty meaningless for an FPGA. And what are these "chips" you're on about?

    --- Quote End ---

    Hello Tricky. I see. For chips, I assume there are some standard chips, and he is wondering how many those standard chips are needed to implement the design. But I am not sure... Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I hope he's not refering the 74 series logic chips. The last time I saw one of those was at university 10 years ago (and on one of my companies' old old boards, about 20 years old). I dont think anyone uses 74 series stuff seriously any more (IIRC, a 74 series chip has about 4 gates on it. Given you have hundreds of thousands of LUTs on modern devices, the number of 74 chips would be silly.)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    I hope he's not refering the 74 series logic chips. The last time I saw one of those was at university 10 years ago (and on one of my companies' old old boards, about 20 years old). I dont think anyone uses 74 series stuff seriously any more (IIRC, a 74 series chip has about 4 gates on it. Given you have hundreds of thousands of LUTs on modern devices, the number of 74 chips would be silly.)

    --- Quote End ---

    Probably something similar to that. I don't think he works in FPGA filed recently. The only reason why I am working on FPGA design is to prove that the algorithm is implementable in hardware. And the algorithm is actually the core of the research.

    I am also pretty sure that when he asked this question he didn't refer to any product of Altera company. He once gave me a very old board from XILINX. May XILINX has standard chips but Altera doesn't?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Nope. Xilinx parts are basically the same as altera. Sounds like he needs to be brought into the new millenium.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Nope. Xilinx parts are basically the same as altera. Sounds like he needs to be brought into the new millenium.

    --- Quote End ---

    So... you mean there were standard chips before, but they don't exist any more today? Then what is the situation now (i.e. what has replaced standard chips)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I have no idea what "standard chips" are meant to mean. There are thousands of types of chip. I just hazarded a guess at what a standard chip was. I suggest you ask him what a "standard chip" is.