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Altera_Forum's avatar
Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

There are no gates on FPGAs, just LUTs. Luts can implement between one and several gates, as its just a look up table. So asking for "gate count" is pretty meaningless for an FPGA. And what are these "chips" you're on about?