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Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation....
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thank you Dave! I have one more question. Is there anything else other than Analysis & Synthesis Resource Usage Summary that can show the hardware usage of my design? My professor keeps asking me how many gates & chips will be needed, but that summary only tells how many ALUTs/LEs are used. Thanks.

David