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No. I am a student and doing some research with a professor. I actually just need to get the waveform to show my professor, since he has asked for that.
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Ok. Its worth making comments like that when you post. It helps the readers of the forum put the question in context and provides an estimate of where you may be in the learning curve.
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I get what you are saying. That definitely is the correct way to test a design.
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Great. Many books on VHDL have very simplistic testbench examples - without clearly stating that the designs are simplistic.
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I am actually implementing a searching & learning algorithm and the only thing that I care about is how many steps a learning agent takes to reach a target. I included the total steps in the waveform (for RTL simulation), and checked that manually... And I am also not checking my design with invalid inputs, since basically I am just doing all these to show that the algorithm can be implemented in hardware. So I only set input variables in my "testbench".
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As an "exercise for the student" I would recommend modifying your testbench to read the number of steps from your logic, and check it against the expected number of steps. Its a good habit to get into, so you may as well start out that way :)
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I wrote the code and tested it with RTL simulation in last summer. And then I was waiting for the professor to get a board to test it in hardware. But now my professor has changed his mind and requested me to run post synthesis simulation to verify everything. So I have no choice but to get the waveform to show him:(
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Then show him you must! But appreciate that your supervisor might not be asking the right questions ... so ask him why, and try to get from him why he thinks seeing the gate-level netlist is important. He may not have a reason, and may assume that if that waveform looks correct, then the design is correct. However, if your waveforms do not exercise the path with the longest delay, you will not see a transition on the worst-case waveform. That is the whole point of performing a TimeQuest analysis - it tells you what the worst-case path is - and if that delay is less than you need, the design will work in real hardware.
Supervisors are only human. They can only supervise based on their own experience. His may be a little rusty ... bottom line, is your supervisors job is to help you to learn for yourself. I think you're off to a good start, so as far as I am concerned (although he is asking you to produce the wrong data), he is doing his job just fine :)
Cheers,
Dave
Honored Contributor
