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TFPGA
New Contributor
New ContributorMinimum pulse width Violation at Triple-Speed Ethernet Intel FPGA IP Cyclone 10 LP problem (Output Port Rate related)
I am integrating the triple speed ethernet Intel Core into my design and I am having some timing problems. My system is: External Clk125 -> clk125 FPGA pin -> Clock Control -> Triple-Speed Ethernet...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
From the example design that download from the Intel FPGA design store, the timing is clean. You may refer to the following link, and check where is the trigger point for this timing problem.
Regards -SK
TFPGANew Contributor
New ContributorI compiled the "clean build" and it also has timing problems:
