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New Contributor

7 years ago

Minimum pulse width Violation at Triple-Speed Ethernet Intel FPGA IP Cyclone 10 LP problem (Output Port Rate related)

I am integrating the triple speed ethernet Intel Core into my design and I am having some timing problems. My system is: External Clk125 -> clk125 FPGA pin -> Clock Control -> Triple-Speed Ethernet...

SengKok_L_Intel

Regular Contributor

7 years ago

Hi,

From the example design that download from the Intel FPGA design store, the timing is clean. You may refer to the following link, and check where is the trigger point for this timing problem.

https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/intel-cyclone-10-lp-fpga-triple-speed-ethernet-and-intel-on-board-phy-chip-reference-design/

Regards -SK