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Altera_Forum's avatar
Altera_Forum
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11 years ago

Max+Plus II to Quartus, EPM7192

Hi,

I have an old design that uses an EPM7192SQC160-10 and used Max+Plus II software to compile and program the device. I would like to do the same using the Quartus II tool. When I compile the old project, I received an error stating "multiple distinct clock error" which was resolved by adding the secondary clock signal to the sensitivity list of a process. When I program the part with the Quartus II compiled pof the CPLD does nothing. When I use the Quartus II programming tool with the old Max+Plus II compiled pof I return to normal operation. Could the change to the sensitivity list have caused my issue? If so, is there a way to disable this error in Quartus II to behave as a Max+Plus II compiler? Or, could my settings be wrong?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Recent versions of quartus have been producing different logic based on sensitivity lists. But Im guessing with and old part, you are also using an old version of quartus.

    If you do have a change in sensitivity list to work around an error - I suspect the code is rather poorly written. How about posting the code here?

    On a related max+plus 2 compile issues - I once compiled code for an old Flex10k that would compile and work just fine in Max+Plus2, but Quartus complained some memories were being connected illegally. We just stuck with max+plus 2. It's VHDL compile is very rubbish, but with legacy designs its often best to stick with legacy tools, usually due too all the (now considered) poor practices used to make the thing actually work.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Tricky,

    Thanks for the reply, but I found out that I didn't have the .pin file in my project and I needed to manually assign the pins to the proper functions. After doing so, my code compiled and the device was able to work.

    Thanks again!