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m_kumar's avatar
m_kumar
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Maximum Input Clock for FIFO

Hi

Iam using max10 fpga , having dought regarding to fifo memory block, what is the maximum input clock can be given to fifo ip.

In my project iam using fifo dual clock mode.

write clock = 240 Mhz,

read clock = 60 Mhz,

I studied device data sheet not find any information for the dought.

Thanks in Advance.

4 Replies

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI Manoj,


    The FIFO IP uses the M9K memory component as basic block along with some logic elements. The achievable frequency is determined by overall design in the FPGA.

    The datasheet provide details of M9K block used in FIFO mode for a fixed configuration. This can be considered as the basis for your estimation.

    However, the actual frequency achieved can only be found out from the final Timing Analyzer report.


    Regards,

    Ashlesha


    • m_kumar's avatar
      m_kumar
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Ashlesha,

      I found this details in datasheet here they mentioned that we can give input clock upto 300 MHz.

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Hope you have got answer to what you are looking for. Is it ok to close this case?


    Regards.


    • m_kumar's avatar
      m_kumar
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi ,

      I have changed my design and reduced input clock to 80Mhz, now i am moving with the project. Anyway thanks for the information.

      Regards

      Manoj