Forum Discussion
m_kumar
Occasional Contributor
Occasional ContributorMaximum Input Clock for FIFO
Hi
Iam using max10 fpga , having dought regarding to fifo memory block, what is the maximum input clock can be given to fifo ip.
In my project iam using fifo dual clock mode.
write clock = 2...
Ash_R_Altera
Regular Contributor
Regular ContributorHI Manoj,
The FIFO IP uses the M9K memory component as basic block along with some logic elements. The achievable frequency is determined by overall design in the FPGA.
The datasheet provide details of M9K block used in FIFO mode for a fixed configuration. This can be considered as the basis for your estimation.
However, the actual frequency achieved can only be found out from the final Timing Analyzer report.
Regards,
Ashlesha
m_kumarOccasional Contributor
Occasional ContributorHi Ashlesha,
I found this details in datasheet here they mentioned that we can give input clock upto 300 MHz.
