MAX10: Dual purpose pins DCLK, nCSO, DATA[0], DATA[1]

Hello,

meassage lines starting with "info" are no warnings, just processing information. The warning about incomplete I/O assignments can be traced in the Fitter report/Resource Section/I/O Standards Section/I/O Assignments Warnings. You'll find hints like missing drive strength or missing location assignment for specific pins.

You should have a .sdc file that at least declares the pin and frequency of your clock input. This enables the timing analyser to check the internal timing of your design.

Frank

This is what I find in the I/O Assignment Warnings:

This is the list in pin planner:

The assignment editor:

And the top vhdl:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Counter_pack.all;

entity counter is

 	port (
	
	ResetxSBI    		: in  std_logic;		
	ClkxCI      		: in  std_logic;
   LedxDO     			: out std_logic_vector(7 downto 0)
	
	);
	
end counter;


architecture behavioral of counter is

	signal CountValuexD						    : unsigned(COUNTER_WIDTH-1 downto 0); -- count value
	
begin  

	CntStateMachine: process (ClkxCI,ResetxSBI)
	begin
		if ResetxSBI = '0' then   

			CountValuexD <= to_unsigned(0,COUNTER_WIDTH);
			
		elsif ClkxCI'event and ClkxCI = '1' then  
			
			-- determine next counter value
			CountValuexD <= CountValuexD + to_unsigned(1,COUNTER_WIDTH);
			
		end if;
	end process CntStateMachine;
	
	-- assign outputs
	LedxDO <= std_logic_vector(CountValuexD(COUNTER_WIDTH-1 downto COUNTER_WIDTH-8));


end behavioral;

The mesage incomplete set of assignments seems to refer to the only two inputs of the design. The outputs seem to be OK. But I don't understand what's missing.

clk_clk and reset_reset_n don't even appear in your design. Do you have any idea where these are coming from?

Hi,

Do you still the warning massage in the I/O Assignment Warnings?