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Gaston's avatar
Gaston
Icon for New Contributor rankNew Contributor
3 years ago

MAX10: Dual purpose pins DCLK, nCSO, DATA[0], DATA[1]

Hey everyone I'm at the very beginning of a project where I want to implement a power converter digital controller on a MAX10 device. I have a little experience, but only with Lattice FPGAs and to...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,

meassage lines starting with "info" are no warnings, just processing information. The warning about incomplete I/O assignments can be traced in the Fitter report/Resource Section/I/O Standards Section/I/O Assignments Warnings. You'll find hints like missing drive strength or missing location assignment for specific pins.

You should have a .sdc file that at least declares the pin and frequency of your clock input. This enables the timing analyser to check the internal timing of your design.

Frank