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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

MAX 10 SC and RAM blocks

In our design some RAM blocks are being inferred from our VHDL (no altera IP is being used).

When targeting the device 10M16SCU169A7G and trying to compile the following error occurs:

Error (16021): You specified a configuration mode that includes memory initialization, however memory initialization is not supported by the selected device. In the Device and Pin Options dialog box, choose a configuration mode without memory initialization.

After following the intructions and selecting "Single Image", we run into the next error in the assembler:

Error (14703): Invalid internal configuration mode for design with memory initialization

Doing some research points out to the issues with MAX 10 SC boards and memory initialization issues:

https://www.alteraforum.com/forum/showthread.php?t=56869

I though this was only with ROM blocks, Is it possible the inferred RAM blocks also trigger the same issue?, or perhaps I am missing a setting?

If this is in fact the issue, then is there any known workaround?

Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Hi,

    1. Can you provide your design so that we can replicate the issue?

    2. Which Quartus Edition & Version are you using?

    3. Please check with below link,

    https://www.altera.com/support/support-resources/knowledge-base/component/2017/error--14703---invalid-internal-configuration-mode-for-design-wi.html

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)
    • fogl's avatar
      fogl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      I will continue on this topic:

      Why Quartus reports an Error (14703) and does not show the problematic file/line? I am using the same code on xilinx and intel FPGAs, and i am always having problem with this initialization with Quartus. I comment out all the ram initialization lines i found in my project ( signal mem : memory_type :=(others => (others => '0')); to signal mem : memory_type;) but i am still getting this error with no additional information and i cannot find another instance of initialized memory in my code.

      So again: Why Quartus reports an Error (14703) and does not show the problematic file/line?