Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMAX 10 SC and RAM blocks
In our design some RAM blocks are being inferred from our VHDL (no altera IP is being used). When targeting the device 10M16SCU169A7G and trying to compile the following error occurs: ...
Altera_ForumHonored Contributor
Honored ContributorThanks Vikas!# 3 did the trick.
fogl
Occasional Contributor
Occasional ContributorI will continue on this topic:
Why Quartus reports an Error (14703) and does not show the problematic file/line? I am using the same code on xilinx and intel FPGAs, and i am always having problem with this initialization with Quartus. I comment out all the ram initialization lines i found in my project ( signal mem : memory_type :=(others => (others => '0')); to signal mem : memory_type;) but i am still getting this error with no additional information and i cannot find another instance of initialized memory in my code.
So again: Why Quartus reports an Error (14703) and does not show the problematic file/line?
