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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

MAX 10 SC and RAM blocks

In our design some RAM blocks are being inferred from our VHDL (no altera IP is being used). When targeting the device 10M16SCU169A7G and trying to compile the following error occurs: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Thanks Vikas!# 3 did the trick.

  • fogl's avatar
    fogl
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I will continue on this topic:

    Why Quartus reports an Error (14703) and does not show the problematic file/line? I am using the same code on xilinx and intel FPGAs, and i am always having problem with this initialization with Quartus. I comment out all the ram initialization lines i found in my project ( signal mem : memory_type :=(others => (others => '0')); to signal mem : memory_type;) but i am still getting this error with no additional information and i cannot find another instance of initialized memory in my code.

    So again: Why Quartus reports an Error (14703) and does not show the problematic file/line?