Making a process

--- Quote Start ---

Hello

A B C K(A,B,C)

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

With the truth table above,how can I make a process?

A,B,C need to be a vector

ABC are the in ports

F is the out port

thanks!

--- Quote End ---

method 1(brute force):

process(A,B,C)

begin

if A = '0' and B = '0' and C = '0' then

F <= '0';

elsif...

....

end if;

end process;

method2:

process(A,B,C)

begin

F <= A or B or C;

if (A = '1' and B = '0' and C = '1') or (A = '1' and B = '1' and C = '0') then

F <= '0';

end if;

end process;

and so on...

end process;

Using VHDL-2008 it becomes even more simple and elegant:

process(all)
begin
   if not(A) or not(B) or not(C) then
      F <= '0';
   elsif .. . 

I have found that VHDL 2008 makes code more readable in this way.

Best, James

--- Quote Start ---

method 1(brute force):

process(A,B,C)

begin

if A = '0' and B = '0' and C = '0' then

F <= '0';

elsif...

....

end if;

end process;

method2:

process(A,B,C)

begin

F <= A or B or C;

if (A = '1' and B = '0' and C = '1') or (A = '1' and B = '1' and C = '0') then

F <= '0';

end if;

end process;

and so on...

end process;

--- Quote End ---

Thanks for the answers.

I will try!

method 3

ABC <= A & B & C;

process(ABC)

begin

case ABC is

when "000" => F <= '0';

...

end case;

end process;

end method3

--- Quote Start ---

A B C F(A,B,C)

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

--- Quote End ---

An alternative option is to use a function call. Your inputs ABC are the index into an 8 entry table, so ...

function lookup(A, B, C : std_logic) return std_logic is
   constant K : std_logic_vector(0 to 7) := "01111001";
begin
   return K(to_integer(unsigned(A & B & C)));
end function;

or something close to that anyway (I just typed the code into the forum editor).

If A, B, C and K are multi-bit signals, then your process can loop over them, or you can re-code the function to use vector arguments, or create a function that calls this function.

Cheers,

Dave

NO K sorry,was my mistake,is F.

I am using the method2,but A,B,C needs to be a BIT_vector.

--- Quote Start ---

NO K sorry,was my mistake,is F.

--- Quote End ---

That doesn't change the suggested solutions.

--- Quote Start ---

I am using the method2,but A,B,C needs to be a BIT_vector.

--- Quote End ---

Use a loop, eg., A(i), B(i), C(i), etc, where i is the loop index.

Cheers,

Dave

LIKE this?

entity tabelaverdades is

Port ( D : in BIT_VECTOR(2 DOWNTO 0);

F : out BIT);

end tabelaverdades;

architecture tabelaverdades_arq of tabelaverdades is

begin

cnt:process(A,B,C)

begin

F <= A or B or C;

if (D(0) = '1' and D(1) = '0' and D(2) = '1') or (D(0) = '1' and D(1) = '1' and D(2) = '0') then

F <= '0';

elsif (D(0) = '0' and D(1) = '0' and C(2) = '0') or (D(0) = '0' or D(1) = '0' or D(2) = '0') then

F <= '0';

elsif (D(0) = '0' or D(1) = '1' or D(2) = '0') then

F <= '1';

elsif (D(0) = '0' or D(1) = '1' or D(2) = '1') then

F <= '1';

elsif (D(0) = '1' or D(1) = '0' or D(2) = '0') then

F <= '1';

end if;

end process cnt;

end tabelaverdades_arq;

process(D)
begin
F <= D(0) or D(1) or D(2);
if D = "101" or D = "110" then
    F <= '0';
end if;
end process;

but check orientation of D (relative to A,B,C)

the F <= D(0) or D(1) or D(2); is for what?

thanks