Making a process

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LIKE this?

entity tabelaverdades is

Port ( D : in BIT_VECTOR(2 DOWNTO 0);

F : out BIT);

end tabelaverdades;

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Sorry, I thought you mean A, B, C, and F were bit_vectors.

In the function above the statement (A & B & C) is converting the three inputs to a 3-element vector, i.e., its equivalent to your D input.

However, as Kaz comments, you need to check the order, i.e., D <= A & B & C, or D <= C & B & A.

Cheers,

Dave

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the F <= D(0) or D(1) or D(2); is for what?

thanks

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The or takes care of all the possible results except D = 110 or 101 which is then updated to 0 e.g.

or of 000 = 0

or of 111 = 1

or of 110 = 1 then forced to 0 and so on

Normally compiler will take care of optimising logic but you can help it.

I mean you can use case statement and leave it to tool

case D is

when "000" => F <= '0';

when "001" => F <= '1';

...

My code:

entity tabelaverdades is
    Port ( D : in  BIT_VECTOR(2 DOWNTO 0);
           F : out  BIT);
end tabelaverdades;
architecture tabelaverdades_arq of tabelaverdades is
begin
cnt:process(D)
begin
D <= A & B & C;
case D is
when "000" => F <= '0';
when "001" => F <= '1';
when "010" => F <= '1';
when "011" => F <= '1';
when "100" => F <= '1';
when "101" => F <= '0';
when "110" => F <= '0';
when "111" => F <= '1';
end case;
end process cnt;
end tabelaverdades_arq;

is good?

OK but you don't have A,B,C defined(they are just truth table concept).

here is another way:

case D is

when "000" | "101" | "110" => F <= '0';

when others => F <= '1';

end case;

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ok,now How can I make a benchtest?

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I have been thinking about a test bench for the truth table being discussed in this post. I have developed the following VHDL code to test the logic:

library ieee;

use ieee.std_logic_1164.all;

entity testxx is

end entity;

architecture arch of testxx is

function to_string(sv: Std_Logic_Vector) return string is

use Std.TextIO.all;

variable bv: bit_vector(sv'range) := to_bitvector(sv);

variable lp: line;

begin

write(lp, bv);

return lp.all;

end;

component truthtable is

port(in_a: in std_logic;

in_b: in std_logic;

in_c: in std_logic;

out_f: out std_logic);

end component;

type tvector is array (7 downto 0)

of std_logic_vector(3 downto 0);

constant test_vectors: tvector := ("0000",

"0011",

-- "0101", -- This is correct

"0100", -- This is an error

"0111",

"1001",

"1010",

"1100",

"1111");

signal a,b,c,z_expected: std_logic;

signal z : std_logic;

signal test: std_logic_vector(3 downto 0);

begin

table1:truthtable port map(in_a => a, in_b => b, in_c => c, out_f => z);

process

begin

for i in 7 downto 0 loop

test <= test_vectors(i);

a <= test_vectors(i)(3);

b <= test_vectors(i)(2);

c <= test_vectors(i)(1);

z_expected <= test_vectors(i)(0);

wait for 10 ns;

if (z = not z_expected) then

report "vector=" & to_string(test);

report "z_expected = " & Std_Logic'image(z_expected) & " z = " & Std_Logic'image(z);

end if;

end loop;

wait;

end process;

end architecture;

I would be interested in any comment anyone has on the above test bench.

J :)