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entity tabelaverdades is
Port ( D : in BIT_VECTOR(2 DOWNTO 0);
F : out BIT);
end tabelaverdades;
architecture tabelaverdades_arq of tabelaverdades is
begin
cnt:process(A,B,C)
begin
F <= A or B or C;
if (D(0) = '1' and D(1) = '0' and D(2) = '1') or (D(0) = '1' and D(1) = '1' and D(2) = '0') then
F <= '0';
elsif (D(0) = '0' and D(1) = '0' and C(2) = '0') or (D(0) = '0' or D(1) = '0' or D(2) = '0') then
F <= '0';
elsif (D(0) = '0' or D(1) = '1' or D(2) = '0') then
F <= '1';
elsif (D(0) = '0' or D(1) = '1' or D(2) = '1') then
F <= '1';
elsif (D(0) = '1' or D(1) = '0' or D(2) = '0') then
F <= '1';
end if;
end process cnt;
end tabelaverdades_arq;