LVDS transmitter alignment

Question

Hello,

I am trying to serialize a 15 bits input with an ALTLVDS transmitter and then deserialize it in a different FPGA with an ALTLVDS receiver. The problem I have it is that the output bit of the transmitter is not synchronize with the input clock so when I try to read it with a receiver (the receiver has the same input clock), the 15 bit output is distorted with respect to the input one.

My question is, which parameters I have to use in both the transmitter and the receiver to be able to recover the original input signal?

Thank you very much.

altera_forum · Answer

altLVDS Tx and Rx are source synchronous interface, that the altLVDS Rx received clock, rx_inclock, should comes from altLVDS Tx tx_outclock. It seems to me both are using a common clock, which does not contain information of the word boundary of the transmitted data, as such it is expected that you have bitslip issue.

By the way, the LVDS maximum SERDES factor is 10, so 15 is supposedly invalid.

altera_forum · Answer

Thank you gambit,

I also thought that 16 bits was invalid but if I enable the option "Implement serializer/deserializer circuitry in logic cells ", I can have more than 10 bits. I have checked it and it works expecting the problem with the clock that it is still there even if I use only 10 bits.

So, if I understood correctly, you are telling me that I need to use the output clock of the transmitter in the receiver. The problem is that both devices are in different boards and I only have one bit to send information from the transmitter to the receiver so I can only send the signal, not a clock. But I have a common clock in both boards that I thought I could use to synchronize the data.

Sorry if I am not able to explain very well the problem but I am a beginner in quartus.

altera_forum · Answer

So you are utilizing only one differential pair? It can't work with Altera basic SERDES core.

I see basically two options:

- implement an asynchronous (UART) protocol. It implies oversampling by e.g. a factor of 8 at the receiver. With any Cyclone series FPGA, it can work up to 50, possibly 100 MBPS data rate.

- use synchronous transmission with some kind of clock recovery at the receiver. Unfortunately, clock recovery is provided as a hardware feature only for Altera GBit transvceivers. There are some methods to achieve it in software through dynamic phase alignment or DPA hardware. To allow clock recovery and frame synchronisation, the data encoding must have special properties that are met e.g. by 8b10b.

I guess, the first approach is more suitable for your application, if the data rate is sufficient.

altera_forum · Answer

You can based on a general protocol interface theory. To receive a data correctly with the correct word boundary, you can add header (must be unique, non repeatable from the data) to your initial data for the receiver to decode. This can be easily implemented from the receiver side using shift registers to detect the header.

What FvM had replied will work for sure as it implements certain accepted industrial protocol(s) to make sure the receiver aligns correctly.

altera_forum · Answer

What speed are you running at? What device are you using as a receiver? Can you perform dynamic phase alignment? This would not require that you use the same clock for transmit and receive. However, you would have to limit your packet length.

Jake

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LVDS transmitter alignment

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