Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

LVDS transmitter alignment

Hello, I am trying to serialize a 15 bits input with an ALTLVDS transmitter and then deserialize it in a different FPGA with an ALTLVDS receiver. The problem I have it is that the output bit of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

altLVDS Tx and Rx are source synchronous interface, that the altLVDS Rx received clock, rx_inclock, should comes from altLVDS Tx tx_outclock. It seems to me both are using a common clock, which does not contain information of the word boundary of the transmitted data, as such it is expected that you have bitslip issue.

By the way, the LVDS maximum SERDES factor is 10, so 15 is supposedly invalid.