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Altera_Forum
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15 years ago

LVDS transmitter alignment

Hello, I am trying to serialize a 15 bits input with an ALTLVDS transmitter and then deserialize it in a different FPGA with an ALTLVDS receiver. The problem I have it is that the output bit of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

thank you very much everybody for the replies. I was able to align the stream sending first a header but sometimes the data got misaligned, I mean the alignment is not stable. Now I am trying to reduce the deserialization factor to 8 and use two clocks to send the whole data stream. Compiling and simulating again the code I have found something weird. I am able to align or not depending on the pattern I use to analyze. I mean, with certain patterns I am able to align but not with other ones.

My clock frequency is 20 MHz.

One more question, could I send somebody my code so you can have a look at it?

Thank you very much