LVDS transmitter alignment

So you are utilizing only one differential pair? It can't work with Altera basic SERDES core.

I see basically two options:

- implement an asynchronous (UART) protocol. It implies oversampling by e.g. a factor of 8 at the receiver. With any Cyclone series FPGA, it can work up to 50, possibly 100 MBPS data rate.

- use synchronous transmission with some kind of clock recovery at the receiver. Unfortunately, clock recovery is provided as a hardware feature only for Altera GBit transvceivers. There are some methods to achieve it in software through dynamic phase alignment or DPA hardware. To allow clock recovery and frame synchronisation, the data encoding must have special properties that are met e.g. by 8b10b.

I guess, the first approach is more suitable for your application, if the data rate is sufficient.