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ErinS's avatar
ErinS
Icon for New Contributor rankNew Contributor
4 years ago

LVDS SERDES IP compile error in Stratix10, Quartus Prime Pro 20.3

Hi,

I have a compile error in my Quartus 20.3 project that appears to be within the Intel-generated LVDS SERDES IP. Can you provide additional insight into what the following error indicates as root cause? I believe the complaint is about a connection within the Intel IP:
"The serial pin LVDSOUT for the LVDS SERDES IP instance dsi2_host_phy_top|phy_wrapper|tx_dphy_top|clk_lane_altera|lvds_0|core|arch_inst|channels[0].tx.serdes_dpa_isnt must be pulled up to the top level and cannot fan out to anything else."

This LVDS IP instance is configured as TX, 1 channel, SERDES factor=8 with external PLL.

Thanks,

Erin

I discovered that Quartus believes the LVDSOUT signal is being fanned out because it is not reading the Verilog HDL macro I've set for the project, corresponding to a Verilog `ifdef around the fanned out signal. So I need to modify the question to discover what the proper way is to set a Verilog define in Quartus 20.3. The method I used in Quartus 19.1 does not appear to work (Assignments -> Settings; Verilog HDL Input; Verilog HDL macro; Name: <Verilog define name>, Setting: 1)

4 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    I am not able to reproduce the error for the directive usage. Quartus 20.3 and S10 device is able to consider the macro definition correctly.

    The error may be due to the `else part where tool might be routing the LVDS output to other glue logic and not the pin, because that it is the only possible way it is expecting.


    Regards


    • ErinS's avatar
      ErinS
      Icon for New Contributor rankNew Contributor
      4 years ago

      It appears that setting the Verilog macro wasn't being saved. There is a separate button to do this in the GUI, not just the OK/Apply buttons. Once I was able to confirm it was saved, the fanout issue was resolved. Thank you - Erin

      • BikshuNaik's avatar
        BikshuNaik
        Icon for New Contributor rankNew Contributor
        3 years ago

        Hi ErinS,

        I am having the same error as you mentioned in your post, while instantiating the LVDS SERDES IP. I could not understand what is the macro you set for this IP and what have you mentioned in the <verilog define name> (Assignments -> Settings; Verilog HDL Input; Verilog HDL macro; Name: <Verilog define name>, Setting: 1).

        So can you please help me.

        thank you.

  • BikshuNaik's avatar
    BikshuNaik
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi,

    Can someone please help me with the solution for the "The serial pin LVDSOUT for the LVDS SERDES IP instance dsi2_host_phy_top|phy_wrapper|tx_dphy_top|clk_lane_altera|lvds_0|core|arch_inst|channels[0].tx.serdes_dpa_isnt must be pulled up to the top level and cannot fan out to anything else." issue. What is the macro i should set for this LVDSOUT signal so that it won't be consider being fanned out.

    Thanks.