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ErinS's avatar
ErinS
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5 years ago

LVDS SERDES IP compile error in Stratix10, Quartus Prime Pro 20.3

Hi, I have a compile error in my Quartus 20.3 project that appears to be within the Intel-generated LVDS SERDES IP. Can you provide additional insight into what the following error indicates as ro...
BikshuNaik's avatar
BikshuNaik
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4 years ago

Hi,

Can someone please help me with the solution for the "The serial pin LVDSOUT for the LVDS SERDES IP instance dsi2_host_phy_top|phy_wrapper|tx_dphy_top|clk_lane_altera|lvds_0|core|arch_inst|channels[0].tx.serdes_dpa_isnt must be pulled up to the top level and cannot fan out to anything else." issue. What is the macro i should set for this LVDSOUT signal so that it won't be consider being fanned out.

Thanks.